Semiconductor devices are continuously improved to enhance device performance. For example, both smaller device size and higher speed of operation are highly desirable performance targets. Transistors also have been continuously reduced in size. The ability to construct smaller gate structures for complementary metal oxide semiconductor (CMOS) transistors makes it possible to pack more transistors on the same surface area. With the smaller gate structures, the thickness of the gate dielectric has also substantially decreased to 3 nm and below in today's technologies. The principal elements of a typical MOS device are illustrated in FIG. 1a. The device generally includes a semiconductor substrate 101 on which a gate stack is disposed.
The gate stack typically comprises an interfacial layer 109 between the silicon substrate and the gate dielectric layer, gate dielectric layer 110 and a gate electrode 114 disposed on the gate dielectric layer 110. In some circumstances (such as when using a conventional silicon oxide gate dielectric), the interfacial layer 109 may be absent. The gate electrode 114 acts as a conductor. An input signal is typically applied to the gate electrode 114 via a gate terminal (not shown). Heavily doped source/drain regions 102 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). A channel region 103 is formed in the semiconductor substrate beneath the gate electrode 114 and separates source/drain regions 102. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 102. The gate electrode 114 is separated from the semiconductor substrate 101 by the gate dielectric layer 110. The insulating gate dielectric layer 110 is provided to prevent electrical current from flowing directly between the gate electrode 114 and the source/drain regions 102 or the channel region 103.
In the process for producing the gate stack in an IC, the gate dielectric layer is deposited according to any thin film deposition method and the gate electrode is deposited over the dielectric layer. The gate dielectric materials currently investigated are characterized by a high dielectric constant (i.e. high-k material). The gate electrode layer is deposited of a material having low electrical resistance. It is desired that the process for depositing the gate electrode is fast to minimize the time of the manufacturing. Polysilicon is generally used as the gate electrode material. However, problems arise since a depletion layer is formed at the polysilicon-dielectric interface, increasing the equivalent oxide thickness of the gate stack. Therefore, other electrode materials with low resistivity are desired. Furthermore, thin film processes that are compatible with the process for depositing the high-k dielectric layer are needed.
The properties of the transistor critically depend on the thickness and quality of the gate dielectric layer 110. Therefore, the dielectric layer, and even the interfacial layer and the channel region are very sensitive to any impurities diffusing from the gate electrode layer. Furthermore, the gate dielectric layer is exposed to detrimental circumstances, when the process for producing the gate electrode layer comprises use of oxygen or oxygen containing precursors or when use of hydrogen plasma or other method where hydrogen radicals are involved is desired after the deposition of the gate dielectric layer.
In U.S. Pat. No. 6,383,879, Kizilyalli et al. describe the use of a metal etch barrier film, deposited by conventional techniques, between the gate dielectric layer and the gate electrode. However, this gate barrier is a high-k dielectric film, which will despite of its high-k value negativity contribute to the effective electrical thickness of the gate dielectric. In U.S. Pat. No. 6,225,168, Gardner et al. describe formation of a gate dielectric layer and a gate barrier layer by subsequent oxidation and nitridation of a deposited Ti or Ta layer. However, thickness control in this rather complicated process sequence is difficult.
The ultra thin dielectric structure of an interfacial layer and a high-k gate dielectric layer is highly sensitive to oxygen. Oxygen can easily penetrate, for instance through a HfO2 layer of 20-30 Å, increasing the thickness of the interfacial SiO2 layer between the silicon substrate and the high-k dielectric layer. A small increase in thickness of the interfacial SiO2 layer can degrade the equivalent oxide thickness (EOT) enormously.
The deposition of a polysilicon gate electrode directly over the HfO2 gate dielectric damages in part the gate oxide. Therefore, a silicon nitride cap or a silicon oxynitride cap is deposited over the gate oxide. However, such silicon compounds are known to increase the EOT value. In the future, smaller and smaller equivalent oxide thickness (EOT) values are called for and, at the same time, from a process integration point of view a polysilicon gate would be preferred. To avoid the depletion effect caused by polysilicon and the increase in EOT caused by the use of a silicon compound as a barrier, a metal or metal nitride barrier film is desirable over the dielectric instead or a silicon compound layer.
Accordingly, what is needed in the art is a method of forming a gate barrier film on a gate dielectric film that method avoids the problems described above.